The present invention relates to a driving method for an ALIS method dot matrix type AC plasma display panel, comprising first electrodes and second electrodes that are arranged adjacently, extend in the same direction, and execute a light-emitting action in each display cell, and a rib that separates individual display cells, wherein a display line is formed between every pair of the first electrode and the neighboring second electrode. More particularly, the present invention relates to a driving method for an ALIS method dot matrix type AC plasma display panel, and a plasma display apparatus, that can achieve a display of high luminance and high quality.
A plasma display apparatus (PDP apparatus) has been put into practical use as a flat display and is expected to act as a thin display of high-luminance. In Japanese Patent No. 2001893, a PDP apparatus that employs the interlacing method that can realize a display of high resolution at a low cost has been disclosed. While a display line is formed between a pair of two neighboring display electrodes in a conventional PDP apparatus, the present PDP apparatus can double the number of the display lines when the number of the display electrodes is the same, or can realize the number of the display lines with half a number of the electrodes by forming a display line between every pair of a display electrode and its neighboring display electrode. This method is called the ALIS (Alternate Lighting of Surfaces) method.
FIG. 1 is a block diagram that shows the general structure of a conventional PDP apparatus that employs the ALIS method. A plasma display panel 1 comprises plural X electrodes (X1, X2, X3, . . . , X5) and Y electrodes (Y1, Y2, Y3, Y4) arranged adjacently, and plural address electrodes (A1, A2, A3, . . . , Am) arranged in the direction perpendicular to that of the X and Y electrodes, wherein phosphors are arranged at the crossings of the electrodes and a discharge gas is sealed in between the two substrates. An address electrode drive circuit 2 applies an address pulse to the address electrode, a scan electrode drive circuit 3 applies a sustain discharge (sustain) pulse as well as applying sequentially a scan pulse to the Y electrode, a sustain electrode drive circuit 4 applies a sustain discharge (sustain) pulse to the X electrode, and a control circuit 5 controls each part. Since the detailed structure and operations of the PDP apparatus that employs the ALIS method have been disclosed in Japanese Patent No. 2001893, a more detailed description is not given here.
FIG. 2 is a diagram that shows the display lines in a normal type PDP apparatus that employs the ALIS method. As described above, in the PDP apparatus that employs the ALIS method, a display is achieved by the interlacing method used widely in such as a TV receiver, wherein odd-numbered display lines 1, 3, 5, . . . are displayed in the odd field and even-numbered display lines 2, 4, 6, . . . are displayed in the even field. In other words, (2N−1) (N is an integer equal to or greater than 1) display lines are displayed in the odd field and the 2N (N is an integer equal to or greater than 1) display lines are displayed in the even field. In order to obtain 2N display lines in a PDP apparatus that employs the ALIS method, (2N+1) X electrodes and 2N Y electrodes are formed. As the X electrode and the Y electrode have an identical shape and light emission for display is executed by a sustain discharge between them, the X electrodes and the Y electrodes are called the display electrodes here.
The normal plasma display panel (PDP) that employs the ALIS method is equipped with a rib between the address electrodes in parallel thereto so that light emission in the lit cell does not propagate to the neighboring cells in the direction in which the display electrode extends. It is, however, designed so that discharge is prevented from propagating in the direction in which the address electrode extends by suppressing the difference in voltage between the display electrodes (X electrodes and Y electrodes) in the unlit rows rather than by providing a rib between display electrodes.
FIG. 3A and FIG. 3B show the state of discharge in the normal PDP apparatus that employs the ALIS method. As shown in FIG. 3A, a discharge is caused to occur to emit light between a Y electrode and the X electrode located above by one in the odd field, and as shown in FIG. 3B, a discharge is caused to occur to emit light between a Y electrode and the X electrode located below by one in the even field. As described above, the discharge will propagate beyond the electrode to the neighboring display row (unlit row) because no rib is provided between the display electrodes.
However, the ALIS method PDP apparatus that does not have a rib between the display electrodes, as described above, prevents discharge from propagating in the direction in which the address electrode extends by preventing a large voltage from being applied between the display electrodes in unlit rows, therefore, a problem is caused that circuits are difficult to design and light emission efficiency is low because it is impossible to increase the driven electrode applied voltage to be applied between the display electrodes.
The present applicants, therefore, have disclosed the ALIS method dot matrix type AC plasma display panel (PDP) and the PDP apparatus in which individual display cells are separated by providing the grid-shaped rib in Japanese Patent Application No. 2000-304404. FIG. 4 is a diagram that shows the cell structure of a dot matrix type PDP. As shown schematically, plural display electrodes composed of a transparent electrode 12 and an opaque metal electrode 13 are arranged at equal intervals on a glass substrate 11 and a dielectric layer 14 and a protective film 15 are provided thereon. On the other glass substrate 19, plural address electrodes A are arranged, a dielectric layer 17 is formed thereon, and moreover, a grid-shaped rib 16 is formed. Each part of the grid-shaped rib 16 corresponds to a mid line between the address electrodes A and the metal electrode 13. On the dielectric layer 17 that is defined by the rib 16, phosphors 18R, 18G, and 18B of three colors R, G, and B, respectively, are formed. The glass substrates 11 and 19 are bonded to each other and a discharge gas is sealed in therebetween.
FIG. 5 is a diagram that shows the pattern of the rib of the dot matrix type PDP with the structure shown in FIG. 4. As shown schematically, the rib 16 has a grid shape, each part of which is located on a mid line between the address electrodes A and the metal electrode 13. Each part defined by the rib 16 corresponds to each display cell. It is similar to the ALIS method PDP in that one display electrode is shared by two neighboring display lines.
The dot matrix type PDP has advantages in that the circuit design is simple and the light emission efficiency is high because discharge is prevented from propagating beyond the range of each display cell defined by the rib, therefore, the driven electrode applied voltage to be applied between the display electrodes can be increased. Moreover, it is possible for the dot matrix type PDP to execute a display not only by the interlacing method but also by the progressive method in which every display row is displayed simultaneously. On the other hand, in order to form 2N display lines, all that is required is to provide (2N+1) display electrodes, as in the case of the conventional ALIS method.
FIG. 6A and FIG. 6B are diagrams that show the state of discharge when the dot matrix type PDP is driven by the interlacing method. As shown in FIG. 6A, odd-numbered display lines are displayed in the odd field and even-numbered display lines are displayed in the even field as shown in FIG. 6B. As obvious from the figure, the discharge range does not increase because it is defined by the ribs and the range of light emission becomes small. Because of this, a problem occurs that luminance is lowered, compared to the case where the conventional ALIS method PDP shown in FIG. 3A and FIG. 3B is driven by the interlacing method.
Japanese unexamined Patent Publication (Kokai) No. 10-133621 has disclosed a technique that can perform the non-interlaced display instead of the interlaced display by writing data of a line simultaneously into two lines when interlaced signals are displayed because there is no display information in non-display rows in each of the odd-numbered and even-numbered fields. If this technique is applied to drive a dot matrix type PDP, luminance can be raised because the display area is extended substantially. When the technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-133621 is applied to drive a dot matrix type PDP, it is easy to write the same data into the both display cells on both sides of a Y electrode by keeping an identical voltage being applied to the X electrodes on both sides of the Y electrode (scan electrode). As a result, the same display data is displayed in the two display lines on both sides of each Y electrode both in the odd field and in the even field.
FIG. 7 is a diagram that shows the display lines when the technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-133621 is applied to drive a dot matrix type PDP. In the odd field, the (2N−1) th data is displayed in the (2N−1) th and the 2N th display lines, and the 2N th data is displayed in the (2N−1) th and 2N th display lines in the even field. In other words, both the (2N−1) th data and the 2N th data are displayed in the same position.
The (2N−1) th data and the 2N th data, however, should be displayed, being shifted by one row from each other, and if displayed being shifted, the frame resolution is not degraded but if displayed as shown in FIG. 7, the centers of display that display different information coincide in the odd field and in the even field, and a problem is caused that the frame resolution is degraded by half.